![]() There are seven processor modes in total: six privileged modes ( abort, fast interrupt request, interrupt request, supervisor, system, and undefined) and one nonprivileged mode ( user). Conversely, a nonprivileged mode only allows read access to the control field in the cpsr but still allows read-write access to the condition flags. #Arm assembly readwrite fullEach processor mode is either privileged or nonprivileged: A privileged mode allows full read-write access to the cpsr. The processor mode determines which registers are active and the access rights to the cpsr register itself. CHRIS WRIGHT, in ARM System Developer's Guide, 2004 2.2.1 PROCESSOR MODES When combining the condition code and the “s” suffix, the condition code comes first, for example,ĪNDREW N. …will store register r4 only if the contents of registers r2 and r3 are equal. The compare (cmp) instruction can be used to set the status bits without any other side effect. …will decrement register r2 and store r3 only if the new value of r2 is zero. In other words, an instruction whose condition code is evaluated to false will not change the state of the processor, such as writing a result register to changing the PC.įor example, the ldreq instruction will only execute if the Z-bit in the CPSR is set, which will be the case if the most recent computational instruction resulted in a result of zero. ![]() Nearly all ARM instructions can include an optional condition code that determines if the instruction will be executed or skipped over. For example, the “ adds” instruction will modify the status bits but the “ add” instruction will not. ![]() The bits are set according to the most recently executed ALU instruction that includes the special “s” suffix. These bits can be used for conditional execution of subsequent instructions. Bakos, in Embedded Systems, 2016 1.5.2 Status registerĪRM v6/v7 maintains a status register called the CPSR ( current program status register) that holds four status bits, negative (N), zero (Z), carry (C), and overflow (O). ![]()
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